AZ100E142 register equivalent, ecl/pecl 9-bit shift register.
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* 700 MHz Minimum Shift Frequency 9-Bit for Byte-Parity Application Asynchronous Master Reset Dual Clocks Operating Range of 4.2V .
in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 .
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts .
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